Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. The individual wafers are subjected to a number of processing operations to reduce the thickness of the wafer, remove damage caused by the slicing and/or other processing operations, and to create at least one highly reflective surface (e.g., on a front surface of the wafer).
In addition to having at least one highly reflective surface, semiconductor wafers for advanced applications preferably have edges that are smooth, damage-free, and polished. Damaged edges may cause edge slip during thermal processing of the wafer. In addition, rough or pitted edges may trap particles that can be later released in a wet cleaning bath. The released particles may then undesirably migrate to the surface of the wafer. Furthermore, various films are deposited onto the wafer surface in some applications, which may deposit at the edge of the wafer. If the edge is not sufficiently smooth, residual film deposits at the edge may flake off. The flakes may come into contact with the surface of the wafer thereby causing surface defects. Conventional silicon wafer processing typically includes an edge treatment operation (e.g., polishing or etching) to provide edges that are sufficiently smooth.
Prior to edge treatment, silicon wafers are typically subjected to a lapping or grinding operation to provide a wafer of the desired flatness, followed by an etching operation (acidic or caustic) to produce a wafer having desired surface roughness. After the flattening and etching operations, the wafers are typically subjected to a double-sided polishing operation to provide smooth front and back wafer surfaces.
In edge polishing operations, wafer edges, including any orientation notch or flat, are typically polished by applying silica to a polishing pad or other surface that is pressed against the wafer edge. Generally, these polishing operations are carried out at a separate station and involve removing dry wafers from a process cassette, aligning the notches in the wafers, polishing the notch in the wafers, polishing the edge of the wafers, scrubbing and/or cleaning the wafers, spin drying the wafers, and then returning the dry wafers to the process cassette where the wafer can be moved to the next station. While edge polishing has proven effective, this operation increases processing time and cost.
Edge etching operations typically include directing an etchant to the edge of the silicon wafer, typically to that portion of the surface extending from the peripheral edge to the flat portion of the wafer surface. Prevention of significant contact of the etchant with the flat portion of the wafer surface is addressed by various methods. These methods include supporting the wafer on a chuck and directing the etchant to the edge of the wafer surface. However, in these types of methods, it may be difficult to etch the peripheral edge of the wafer within the contour of a wafer notch. Various other methods involve stacking wafers together, often including gaskets between adjacent wafers, and directing the etchant to the exposed edge portion of the wafer. One disadvantage of these types of edge etching operations is difficulty in separating the wafers after etching.
Recent advances in grinding technology provide flatter wafers with improved nanotopology, and the grinding surface depth has become more uniform and shallow. In addition, recent double-sided polishing operations offer the advantage of removal of small amounts of subsurface damage on both sides of the wafer. In fact, increased stock removal by double-sided polishing may increase the burden on the edge treatment (e.g., polishing) operation.
Thus, there remains an unfulfilled need for a wafer edge treatment method that addresses the disadvantages of current edge treatment operations and is suitable for use in wafer processing operations utilizing recent developments in various aspects of wafer processing (e.g., grinding and/or double-sided polishing).